SHORT  L2 data TLB miss rate/ratio

EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
PMC0  DTLB_LOAD_MISSES_CAUSES_A_WALK
PMC1  DTLB_STORE_MISSES_CAUSES_A_WALK
PMC2  DTLB_LOAD_MISSES_WALK_DURATION
PMC3  DTLB_STORE_MISSES_WALK_DURATION

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  FIXC1/FIXC0
L1 DTLB load misses     PMC0
L1 DTLB load miss rate  PMC0/FIXC0
L1 DTLB load miss duration PMC2
L1 DTLB store misses     PMC1
L1 DTLB store miss rate  PMC1/FIXC0
L1 DTLB store miss duration PMC3

LONG
Formulas:
L1 DTLB load misses     DTLB_LOAD_MISSES_CAUSES_A_WALK
L1 DTLB load miss rate  DTLB_LOAD_MISSES_CAUSES_A_WALK / INSTR_RETIRED_ANY
L1 DTLB load miss duration DTLB_LOAD_MISSES_WALK_DURATION
L1 DTLB store misses     DTLB_STORE_MISSES_CAUSES_A_WALK
L1 DTLB store miss rate  DTLB_STORE_MISSES_CAUSES_A_WALK / INSTR_RETIRED_ANY
L1 DTLB store miss duration DTLB_STORE_MISSES_WALK_DURATION
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The DTLB load and store miss rates gives a measure how often a TLB miss occurred
per instruction. The duration measures the time in cycles how long a walk did take.

